A shift calculator is used for performing logical shift or arithmetic shift. A shift calculator which has an input/output data width of 64 bits and a shift amount of 0 to 63 bits has a right shift function and left shift function, and performs logical shift and arithmetic shift. With regard to parity protection, parity propagation is assumed. In the event that input data and input parity are unmatched, output data and output parity will be unmatched at some point following shifting.
FIG. 1 is a diagram illustrating an example the configuration of a 64-bit left/right shifter. The left/right shifter 1 has a 64-bit right shifter 2, a 64-bit left shifter 3 and a selector 4. The shifters 2 and 3 receive 64-bit input data and 6-bit shift amounts. The selector 4 selects the shift results of one of the shifter 2 or the shifter 3 in accordance with a selection signal, and outputs as 64-bit output data.
FIG. 2 is a diagram illustrating an example of a right shifter 2. The right shifter 2 has right shifters 2-1, 2-2, and 2-3 of which shift amount of 2 bits is input. The right shifter 2-1 shifts with width of 0, 1, 2, and 3 bits, the right shifter 2-2 shifts with width of 0, 4, 8, and 12 bits, and the right shifter 2-3 shifts with width of 0, 16, 32, and 48 bits.
FIG. 3 is a diagram illustrating an example of a left shifter 3. The left shifter 3 has left shifters 3-1, 3-2, and 3-3 of which shift amount of 2 bits is input. The left shifter 3-1 shifts with width of 0, 1, 2, and 3 bits, the left shifter 3-2 shifts with width of 0, 4, 8, and 12 bits, and the left shifter 3-3 shifts with width of 0, 16, 32, and 48 bits.
The shifters 2 and 3 may be formed of rotator shifters.
FIG. 4 is a diagram illustrating an example of a left/right shifter operating at 2τ cycle. The left/right shifter 11 illustrated in FIG. 4 is used with microprocessors having a relatively high operating frequency, for example. While the left/right shifter 11 basically uses the same operating principle as the shifter 1 illustrated in FIG. 1, the shifters formed in three stages as illustrated in FIGS. 2 and 3 are divided into two portions, with a latch circuit provided between the divided shifters.
The left/right shifter 11 has a conversion circuit 12 for converting 1-byte parity into 4-bit parity, first through third right shifters 13-1 through 13-3, first through third left shifters 14-1 through 14-3, a selector 15, a 64+16-bit latch circuit 16, a conversion circuit 17 for converting 4-bit parity into 1-byte parity, a selector 18, 1-bit latch circuits 19 and 20, and a 4-bit latch circuit 21. In FIG. 4, SRA denotes a signal indicating arithmetic right shift, D[63:0] denotes input data, DP[7:0] denotes input parity, SELR denotes a left/right selection signal, SA denotes a signal indicating shift amount, and RSGN denotes a bit for the sign SIGN. SA2 indicates the 2τ′th shift amount, with the upper 4 bits of the shift amount SA having been latched at the latch circuit 21, while RSGN2 indicates the bit RSGN of the sign SIGN generated the 1τ′th shift latched at the latch circuit 19.
In order to reduce the number of bits at the latch circuit 16, the shift results of the first shifters 13-1 and 14-1 are selected at the selector 15 in response to the left/right selection signal SELR, and stored in the latch circuit 16, when the 1τ′th shift at the first shifters 13-1 and 14-1 has ended. Thus, for the 1τ′th shift, the first shifters 13-1 and 14-1 are used to perform right shift and left shift of 0, 1, 2, and 3 bits. Also, for the 2τ′th shift, the second and third shifters 13-2, 14-2, 13-3, and 14-3, are used to perform 0 to 60 bit right shift and left shift in 4-bit increments. For the 2τ′th shift, the second shifters 13-2 and 14-2 are used to perform 0, 4, 8, and 12 bit right shift and left shift, and the third shifters 13-3 and 14-3 are used to perform 0, 16, 32, and 48 bit right shift and left shift, with the shift results of the third shifters 13-3 and 14-3 being selected by the selector 18 and in response to the left/right selection signal SELR, and output.
The left/right selection signal SELR, the arithmetic right shift signal SRA, and the sign SIGN bit RSGN satisfy a relationship such as illustrated in FIG. 5, in accordance with shift conditions.
FIGS. 6 through 7B are circuit diagrams illustrating an example of the first shifters 13-1 and 14-1. To facilitate description, only signals relating to the input data D are illustrated in FIGS. 6 through 7B. The first shifters 13-1 and 14-1 generate selection signals S0 through S3 from 2-bit shift amount SA[1:0], by a circuit unit having two inverters 131 and four AND circuits 132 connected as illustrated in FIG. 6. The first shifter 13-1 includes 64 4-to-1 selectors using AND-OR circuits having four AND circuits 133 and one OR circuit 134 as illustrated in FIG. 7A. The first shifter 14-1 includes 64 4-to-1 selectors using AND-OR circuits having four AND circuits 143 and one OR circuit 144 as illustrated in FIG. 7B. RR represents the results of logical or arithmetic right shift (right shift of 0, 1, 2, and 3 bits) by the right shifter 13-1, and LR represents the results of logical or arithmetic right shift (left shift of 0, 1, 2, and 3 bits) by the left shifter 14-1.
FIGS. 8 through 9B are circuit diagrams illustrating an example of the second shifters 13-2 and 14-2. To facilitate description, only signals relating to the output data SD of the latch circuit 16 are illustrated in FIGS. 8 through 9B. The second shifters 13-2 and 14-2 generate selection signals S0, S4, S8 and S12 from 2-bit shift amount SA2[1:0], by a circuit unit having two inverters 135 and four AND circuits 136 connected as illustrated in FIG. 8. The second shifter 13-2 includes 64 4-to-1 selectors using AND-OR circuits having four AND circuits 137 and one OR circuit 138 as illustrated in FIG. 9A. The second shifter 14-2 includes 64 4-to-1 selectors using AND-OR circuits having four AND circuits 147 and one OR circuit 148 as illustrated in FIG. 9B. R2D represents the results of logical or arithmetic right shift (right shift of 0, 4, 8, and 12 bits) by the second right shifter 13-2, and L2D represents the results of logical or arithmetic right shift (left shift of 0, 4, 8, and 12 bits) by the second left shifter 14-2.
FIGS. 10 through 11B are circuit diagrams illustrating an example of the third shifters 13-3 and 14-3. To facilitate description, only signals relating to the output data R2D and L2D of the second shifters 13-2 and 14-2 are illustrated in FIGS. 10 through 11B. The third shifters 13-3 and 14-3 generate selection signals S0, S16, S32 and S48 from 2-bit shift amount SA2[3:2] by a circuit unit having two inverters 139 and four AND circuits 140 connected as illustrated in FIG. 10. The third shifter 13-3 includes 64 4-to-1 selectors using AND-OR circuits having four AND circuits 141 and one OR circuit 142 as illustrated in FIG. 11A. The third shifter 14-3 includes 64 4-to-1 selectors using AND-OR circuits having four AND circuits 151 and one OR circuit 152 as illustrated in FIG. 11B. R3D represents the results of logical or arithmetic right shift (right shift of 0, 16, 32, and 48 bits) by the third right shifter 13-3, and L3D represents the results of logical or arithmetic right shift (left shift of 0, 16, 32, and 48 bits) by the third left shifter 14-3.
As for parity, four bit parities of performing 0-bit, 1-bit, 2-bit, and 3-bit right shift and left shift are each generated for the 1τ′th shift, and 4-bit parity corresponding to shifted data is selected using a 4-to-1 selector having AND-OR circuits such as illustrated in FIG. 7. With regard to one arbitrary byte, right shift 4-bit parity RP[1:0] and left shift 4-bit parity LP[1:0] are obtained from data D[7:0] and byte parity DP (EOR (Exclusive-OR) of D[7:0]) as follows.
FIG. 12 illustrates the right shift 4-bit parity RP[1:0] in the case of right shift.
FIG. 13 illustrates the left shift 4-bit parity LP[1:0] in the case of left shift.
The shift amount of 0 to 3 bits is illustrated as SA[1:0], data one byte above the object byte as DH[7:0], and data one byte below as DL[7:0]. Also, for the 2τ′th shift, byte parities of having performed right shift and left shift of 0 and 4 bytes are generated from 4-bit parity from the latch circuit 16, and byte parities corresponding to the data shifted by shifting with the second and third shifters 13-2, 14-2, 13-3, and 14-3, are obtained.
First, the parity shift corresponding to right shift of data by 0, 4, 8, and 12 bits is obtained as illustrated in FIG. 14 with byte parity at the time of 0 bit right shift as R0BP[7:0] and byte parity at the time of 4 bit right shift as R4BP[7:0].
The byte parity at the time of 8-bit right shift is equivalent to the 8 bits of 0,R0BP[7:1], and the byte parity at the time of 12-bit right shift is equivalent to the 8 bits of 0,R4BP[7:1]. Therefore, the second right shifter 13-2 may select R0BP[7:0] and R4BP[7:0].
Also, the parity shift corresponding to right shift of data by 0, 16, 32, and 48 bits is the same as 0, 2, 4, and 6 bit shift of 8-bit data, since this is a byte (8-bit) parity shift. If expressing the parity following shifting at the third right shifter 13-3 as RBP[7:0], RBP[2:1] for example is as illustrated in FIG. 15.
Next, the parity shift corresponding to left shift of data by 0, 4, 8, and 12 bits is obtained as illustrated in FIG. 16 with byte parity at the time of 0 bit left shift as L0BP[7:0] and byte parity at the time of 4 bit left shift as L4BP[7:0].
The byte parity at the time of 8-bit left shift is equivalent to the 8 bits of L0BP[6:0], 0, and the byte parity at the time of 12-bit left shift is equivalent to the 8 bits of L4BP[6:0], 0. Therefore, the second left shifter 14-2 may select L0BP[7:0] and L4BP[7:0].
Also, the parity shift corresponding to left shift of data by 0, 16, 32, and 48 bits is the same as 0, 2, 4, and 6 bit shift of 8-bit data, since this is a byte (8-bit) parity shift. If expressing the parity following shifting at the third left shifter 14-3 as LBP[7:0], LBP[7:6] for example is as illustrated in FIG. 17.
The above related art is described in Japanese Unexamined Patent Application Publication No. 60-233729 and Japanese Unexamined Patent Application Publication No. 62-115529.
The above-described shift calculator has multiple stages, so not only is the circuit scale great, but also the standby power, or static power, is great. Further, there has been problem in that with shift calculators having right shift circuits and left shift circuits, even if one side is being used the other side wastes active power, or dynamic power, due to circuit operations. While an arrangement can be made with a rotator configuration as described in Japanese Unexamined Patent Application Publication No. 60-233729, the number of logical states from input to output is great, and there has been a problem that timing penalty is great.